Forum Discussion
MinzhiWang
Occasional Contributor
Occasional ContributorQuestion about normal differential I/O input ports pairs to Cyclone 10 GX interconnection
Hello guys, We are using 10CX220YF780E5G devices in our application. This FPGA mainly receive ADC output data by using LVDS differential pairs interface. I can find many posts here to discuss about ...
AqidAyman_Altera
Regular Contributor
Regular ContributorBased on the pin connection guideline, the pin that you used to connect the Trigger_pair are the true LVDS receiver/transmitter channels.
Refer to this link: https://www.intel.com/content/www/us/en/docs/programmable/683417/current/differential-i-o-pins.html
MinzhiWangOccasional Contributor
Occasional ContributorHello AqidAyman,
Are there any materials about how to connect CML pairs to FPGA lvds pairs?
