Question about Monitor

Hi Aditya,

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All the problems are now solved. Are there any other designs that you have in mind that would make me more familiar with the software.

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Successful 'simulations' should be followed up by a hardware test that confirms things work. I'd recommend testing your design :)

Cheers,

Dave

Hello Dave,

All the problems are now solved. Are there any other designs that you have in mind that would make me more familiar with the software.

Thanks,

Aditya

Hello Dave,

I get this error "Timing requirements not met" should I even worry about that error. What happens when I synthesize the system on the FPGA.

Thanks,

Aditya

Hello Dave,

Is the PCIe design[the one you sent me] given in a some tutorial or did you come up with your own design?, If it's a given in some manual or study guide can you please give it to me?

Thanks,

Aditya

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When I write data to the txs of the PCIe hard IP using API calls, [eg. addr: 00(starting address of ram) and data= 32'h05], the data is automatically written to the RAM right?

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Not necessarily.

The PCI interfaces I've used generally have to be configured and enabled first. Only then will read and write accesses from the 'outside world' succeed.

That's why you need to start with the Altera example first, since it will contain the initialization sequence. Start with their design, and modify that.

Then once you have the PCI interface working, there will be an address translation phase. If the base address of BAR0 is 0xFF00_0000 in PCIe address space, then you can have accesses to that region decode to your Avalon bus at address 0x0000_0000 (the address translation will depend on a PCIe configuration register). If your RAM is at that address, then the transaction will occur to your RAM. So make sure your PCIe access address is relative to the BAR0 address, not to the addresses in the Avalon-MM address map.

Cheers,

Dave

Hello Dave,

When I write data to the txs of the PCIe hard IP using API calls, [eg. addr: 00(starting address of ram) and data= 32'h05], the data is automatically written to the RAM right?

Thanks,

Aditya

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Can you please tell me the difference between step a and step b of my previous question. That will make me understand things better

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Step (a) includes the statement "Standard, BFMs for standard avalon interfaces", and you need a pcie bfm to test a PCIe design, so (b) is the only solution.

Cheers,

Dave

Hello Dave,

Can you please tell me the difference between step a and step b of my previous question. That will make me understand things better

Thanks,

Aditya

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a) In the Qsys generation tab select the "Standard, BFMs for standard Avalon Interfaces" and the qsys will attach appropriate BFM's to the PCIe IP.

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Unless Qsys gives you the option of adding a PCIe BFM, then this is of no interest to you (just yet).

Go and complete the PCIe reference design first. That should give you a better understanding. Look where they connect their PCIe BFM; its probably outside the Qsys system.

Cheers,

Dave