Hello, is it possible to synthesize the "monitors" on the altera fpgas'. There are Monitor IPs such as Avalon MM Monitor. Can I synthesize such "Monitors"?

--- Quote Start --- is it possible to synthesize the "monitors" on the altera fpgas'. There are Monitor IPs such as Avalon MM Monitor. Can I synthesize such "Monitors"? --- Quote End --- No. The monitors are there to generate assertion messages regarding Avalon-MM bus protocol violations. Cheers, Dave

Thanks Dave. I came across some papers which discussed about developing monitors in SVA [System Verilog Assertion Language] and it stated that these monitors can be synthesized. "This paper presents one implementation of the Open Control Protocol (OCP) monitoring on the synthesized FPGA design using the implemented library of Synthesizable SystemVerilog Assertions (SSVA). The SSVA library is developed using the layer structure of SystemVerilog assertions. It is used in implementation of the monitors for two profiles of the OCP. SSVA library and OCP monitors are then functionally verified in simulator using the test case of the processor-memory communication. The test case is then synthesized on CHIPit Platinum Edition FPGA. The implemented library and monitors can be used in many commercial and educational projects due to their simplicity and low FPGA area usage."

--- Quote Start --- I came across some papers which discussed about developing monitors in SVA [System Verilog Assertion Language] and it stated that these monitors can be synthesized. --- Quote End --- Have a look at the source code. I think you'll find it wrapped in synthesis off/on blocks so that Quartus never even sees the code. That's certainly the case for the Avalon-MM master BFM component. The complication regarding synthesized assertions, is that an assertion needs some method of reporting failures, so a synthesizeable assertion checker would need an Avalon-MM interface with a block of control/status registers so that you could check for assertion failures, and clear error counters. But if your transaction just locked up the Avalon-MM bus, how would you read that register? You really don't want your transactions to fail in real hardware. That is what verification testing is for in the simulator :) Cheers, Dave

Monitors can be synthesized but not recommended right?. I will do some reading and get back to you about this. I have just started Qsys a few weeks ago, apart from the tutorials provided by qsys are there any other online tutorials/ good books about qsys. Thank you, Aditya

--- Quote Start --- Monitors can be synthesized but not recommended right? --- Quote End --- You're missing the point. The task of a monitor is to confirm that components adhere to the bus protocol specification. If a component will violate the bus specification, then its likely the bus will lock-up, and your system will freeze. Sure you can have a watch-dog reset the bus, and perhaps have a 'reset reason' and a backtrace. But all this can be reproduced in the simulation much easier. You setup randomized bus transactions, and code coverage, etc., and make sure things are well tested. Then you can synthesize. --- Quote Start --- I will do some reading and get back to you about this. --- Quote End --- Sure. I'm not saying they don't exist, but the question is what use are they? Feel free to come up with a good reason :) --- Quote Start --- I have just started Qsys a few weeks ago, apart from the tutorials provided by qsys are there any other online tutorials/ good books about qsys. --- Quote End --- You will learn best by building components, constructing _hw.tcl files, and synthesizing them. The nice thing about this approach is that you can get Quartus to generate an _hw.tcl file for some simple components, and then read the documentation about the settings. Things will make much more sense then. The Quartus handbook has chapters on Qsys. I think alot of the component stuff is the same as the SOPC Builder stuff, so you can look at that manual too. The Qsys tutorial has layers of hierarchy, since Altera wants to show off the new features of Qsys relative to SOPC Builder. Rather than using that to learn from, try to create a design with an Avalon-MM BFM master, and an Avalon-MM slave registers interface; don't use the PIO core, write your own. Then write a SystemVerilog testbench to generate read/write transactions to your registers. You can add an Avalon-MM monitor into your testbench, and then generate transactions that violate the bus specification, eg. perform a read or write with invalid byte enables and see the assertion failure messages. You must have a tool that supports System Verilog Assertions (SVA), like the full version of Modelsim, otherwise you will not get the SVA messages. Cheers, Dave

Question about Monitor | Altera Community

117 Replies

Altera_Forum
Honored Contributor
15 years ago
Got it!. All this time I was adding the files that were meant for simulation and had unchecked the synthesis option.
Altera_Forum
Honored Contributor
15 years ago
--- Quote Start ---
The SOPC gives these errors. I'm sorry, can you elaborate on how the _hw.tcl - keywords is responsible for this error.
--- Quote End ---
Look inside your _hw.tcl file for your new component. SOPC builder is complaining about 'start' and 'end' keywords, and something that is defined as a 'start' connection, when it is defined as an 'endpoint'.

I don't use SOPC Builder enough to know what these errors are due to. As I mentioned earlier, I generally let SOPC Builder generate the first version of _hw.tcl and then edit that.

I think you have some interfaces defined incorrectly. Move your _hw.tcl file someplace else, and use component editor to help create a new file. Then get it working. Finally, compare your original _hw.tcl file to the new one to see where you went wrong.

Cheers,
Dave
Altera_Forum
Honored Contributor
15 years ago
The SOPC gives these errors. I'm sorry, can you elaborate on how the _hw.tcl - keywords is responsible for this error.
Altera_Forum
Honored Contributor
15 years ago
--- Quote Start ---
What I don't understand is the missing start/end point in the error message ?

--- Quote End ---
Does SOPC Builder give you this error, or Modelsim? If its SOPC Builder, then these sound like _hw.tcl keywords; check the syntax in your component file.

Cheers,
Dave
Altera_Forum
Honored Contributor
15 years ago
Hello Dave,

I have connected the custom component to "Onchip RAM" and I am able to wire data to the memory. [I first Generate the simulation files in Verilog and attach only the Clock and Reset BFMs. Then using the test bench I write data to the ram using some tasks and observe the result in the memory viewer window] The .tcl file of the component is working fine. What I don't understand is the missing start/end point in the error message ?

Thanks,
E=mc2
Altera_Forum
Honored Contributor
15 years ago
--- Quote Start ---

Error: June10_ram2.ixp465_rwdata_0: Component ixp465_rwdata 1.1 not found

--- Quote End ---
Look in your project; does it include the code for component with pin ixp465_rwdata? Or perhaps this is a typo?

Rather than coding the _hw.tcl file directly, have the component editor automatically generate the _hw.tcl file, and then edit it to customize it. If your code is VHDL, and it includes components, eg., library mylib; use mylib.components.all;, then you'll need to include the 'components' package before your custom component, otherwise Quartus will complain. Iterate a few times, reading the errors, until you get it right.

Before trying to make a component _hw.tcl file based on untested VHDL or Verilog source, make sure it compiles with Modelsim first.

Cheers,
Dave
Altera_Forum
Honored Contributor
15 years ago
The errors are here:

Error: June10_ram2.ixp465_rwdata_0: Component ixp465_rwdata 1.1 not found

Error: June10_ram2.ixp465_rwdata_0.ixp_master/ram.s1: Illegal connection start (ixp465_rwdata_0.ixp_master is an end interface)

Error: Ixp465_rwdata_0.ixp_master/ram.s1: Connection ixp465_rwdata_0.ixp_master/ram.s1 has missing start or endpoint

Error: Ixp465_rwdata_0.ixp_master/ram.s1: Connection ixp465_rwdata_0.ixp_master/ram.s1 has missing start or endpoint
Altera_Forum
Honored Contributor
15 years ago
Hello Dave,

yep figured it out!. Thanks. When i try to compile a a design involving a custom component I get the following errors. The error screen shot is attached. http://www.alteraforum.com/forum/C:\Documents and Settings\aashoka\My Documents\My Pictures\ixp_error.bmp

The .tcl file associated with the custom component is present in the .qsf file [the path is present]. Why is the error still occuring.

Thanks,
Adi
Altera_Forum
Honored Contributor
15 years ago
--- Quote Start ---

What does the error " Error(10744): Verilog HDL error at verbosity_pkg.sv : functions cant enable tasks" mean. The verbosity package is generated by quartus.qsys. I have not modified that file either"

--- Quote End ---
I have not seen that error.

Please check you have enabled SystemVerilog in Modelsim; Compile menu, Compile Options, Verilog&SystemVerilog tab, and make sure SystemVerilog is checked as the language.

Cheers,
Dave
Altera_Forum
Honored Contributor
15 years ago
Hello Dave,

Thanks for you reply!.

What does the error " Error(10744): Verilog HDL error at verbosity_pkg.sv : functions cant enable tasks" mean. The verbosity package is generated by quartus.qsys. I have not modified that file either"

Thanks

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Question about Monitor

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