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Altera_Forum's avatar
Altera_Forum
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15 years ago

Question about Monitor

Hello, is it possible to synthesize the "monitors" on the altera fpgas'. There are Monitor IPs such as Avalon MM Monitor. Can I synthesize such "Monitors"?
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

Hello Dave,

I have connected the custom component to "Onchip RAM" and I am able to wire data to the memory. [I first Generate the simulation files in Verilog and attach only the Clock and Reset BFMs. Then using the test bench I write data to the ram using some tasks and observe the result in the memory viewer window] The .tcl file of the component is working fine. What I don't understand is the missing start/end point in the error message ?

Thanks,

E=mc2