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Altera_Forum
Honored Contributor
Honored ContributorQuestion about Monitor
Hello, is it possible to synthesize the "monitors" on the altera fpgas'. There are Monitor IPs such as Avalon MM Monitor. Can I synthesize such "Monitors"?
Altera_ForumHonored Contributor
Honored ContributorThe errors are here:
Error: June10_ram2.ixp465_rwdata_0: Component ixp465_rwdata 1.1 not found Error: June10_ram2.ixp465_rwdata_0.ixp_master/ram.s1: Illegal connection start (ixp465_rwdata_0.ixp_master is an end interface) Error: Ixp465_rwdata_0.ixp_master/ram.s1: Connection ixp465_rwdata_0.ixp_master/ram.s1 has missing start or endpoint Error: Ixp465_rwdata_0.ixp_master/ram.s1: Connection ixp465_rwdata_0.ixp_master/ram.s1 has missing start or endpoint
