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Altera_Forum's avatar
Altera_Forum
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15 years ago

Question about Monitor

Hello, is it possible to synthesize the "monitors" on the altera fpgas'. There are Monitor IPs such as Avalon MM Monitor. Can I synthesize such "Monitors"?
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

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What does the error " Error(10744): Verilog HDL error at verbosity_pkg.sv : functions cant enable tasks" mean. The verbosity package is generated by quartus.qsys. I have not modified that file either"

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I have not seen that error.

Please check you have enabled SystemVerilog in Modelsim; Compile menu, Compile Options, Verilog&SystemVerilog tab, and make sure SystemVerilog is checked as the language.

Cheers,

Dave