Quartus 14.0 Clock generation

You have used the standard Altera GHRD with/without some changes on Altera CV SoC board ?

Or board is self-made ?

On previous versions of Quartus: 13.1, 13.0sp1, 13.0 also was problems ?

We recompile GHRD in 13.1 with small changes successful.

The board is self made.

WE boot via QSPI (NOR chip EPCQ256)

With Quartus 13.1 it's not possible to use 27MHz. Maybe it is, but then you have to manually adjust the PLL_config.h file.

On rev0 we are using a 5CSEBA5U23I7N with 27MHZ. Because back then, we had only quartus 13.1. we fixed the 27MHz to 25MHz.

After fixing the Clock, the board worked. we used nfs to boot linux.

On rev1 we are using a 5CSEBA4U23C7N with 27MHZ. Because now quartus 14.0 allows you to change the PLL settings. we can enter UBOOT, but running NFS (stable) is not possible. I don't know why. The only thing I can think of is the PLL not locking or the 249.75 MHZ is not good enough.

settings are

Osc1_clk = 27MHz

sclk_out = 27MHz

qspi_clk = 108MHz

mpu_clk = 216 MHz

EMAC = 249.75MHZ

May be problem is not in Quartus clocks ?

My Altera CV Board have 2 Ethernet MACs:

10/100/1000 Ethernet (HPS EMAC) with RGMII connection to PHY at 250 Mbps;

10/100 Ethernet (FPGA internal MAC) with MII connection using 25 Mbps.

You are used first internal HPS EMAC without internal FPGA-core ? Second "soft"-MAC is meaningless ?

HPS EMAC must be worked without FPGA configuration, for example, download .rbf from Internet on Pover On and "bare" FPGA, save it to flash and configure FPGA with it after... Clock 250 to Ethernet system must be given independently from FPGA!

Problem may be in PHY or ways to it in board.

Pinging from board to host (from host) is normal ?

May be PHY "mirror" mode to return all sended from EMAC data back to.

I'm using the HPS EMAC - RGMII.

At the moment i'm doing nothing with the FPGA Fabric.

So the part that is nog working is the configuration of the PHY. One in the many times (on a power cycle), the PHY successfully gets configured. after the PHY is configured, it's no problem to load the Kernel and Rootfs. so i think the the data paths are oke.

The problem lies in the configuration of the PHY.

Also i see, that if the board starts-up in a cycle where the PHY does nothing. I can't even write something to the PHY with UBOOT command - MII Write.

Strange. that sometimes, the PHY gets configured and everything works normaly. I can boot linux form nfs, and do everything i want. But most of the times, the phy doesn't gets configured and i can't get access to the PHY. When i do a MII DUMP , i get 0xFFFF. and can't write back.

You would say, that is the EMAC controller is out of reset and the PHY is out of reset, you could at least do some basic MII WRITE commands.

Any ideas ?

Thanks in advanced.

Is your PHY the same as in Altera kit ?

I yet not found ARM document with MAC description.

SignalTap can't help in these situation, if device registers on the outside of FPGA.

Without sources and recompiling Linux kernel with "while (1) ;" and "-g" in Eth-init codes and connection DS-5 to process of booting may be impossible go forward.

In ug_soc_eds.pdf writed about "Linux driver developing", may be writed "a hack" driver, loaded through DS-5, and go from this to init EMAC function... :)

And last version of DS-5 is very strange and nonstable in execute command "Set PC to Selection" from context menu.

If you press reset buttons after successful starting of EMAC, next init is OK ?

May hack a existing Linux with binary code in order to repeat init EMAC until not OK...

So i made some progress.

with coincidence, i toggled the power source realy quick. like 100 - 200 mili seconds. And there it is. The EMAC runs fine. When i then toggel the power source, only slow, the EMAC does nothing.

Also, when i leave the Ethernet cable in the ethernet jack. and toggle fast, the EMAC does nothing. When i remove the ethernet cable. and toggle fast. The EMAC Works fine.

Just for reference.

I also use custam clock ( not 25MHz) and emac.

my boards are works good.

In my case, we should set emac clock 250MHz exactly.

Qsys can not generate exact 250MHz in case that osc not 25MHz.

Try to change emac clock 250MHz(exactly 250MHz) by "edditing pll_config.h"

So found the problem.

I had the EMAC configured to get out of reset on power good. The HPS uses the same power good. We did this because on a older prototype this solution works. But i geuss it's was no good practice. The EMAC needs a periode after power up in which you must not talk to the EMAC.

So we changed the setup, so now the EMAC powers-up before the HPS. And it works fine.

Thnx for all the hints and tip. Much appreciated.