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Altera_Forum
Honored Contributor
Honored ContributorQuartus 14.0 Clock generation
Hello All, So i have a prototype where we use a 27MHz clock. A problem we are having is that Qsys can't make all the clocks. We can boot as far as UBOOT from NOR flash with CSEL on "10" with ...
Altera_ForumHonored Contributor
Honored ContributorIs your PHY the same as in Altera kit ?
I yet not found ARM document with MAC description. SignalTap can't help in these situation, if device registers on the outside of FPGA. Without sources and recompiling Linux kernel with "while (1) ;" and "-g" in Eth-init codes and connection DS-5 to process of booting may be impossible go forward. In ug_soc_eds.pdf writed about "Linux driver developing", may be writed "a hack" driver, loaded through DS-5, and go from this to init EMAC function... :) And last version of DS-5 is very strange and nonstable in execute command "Set PC to Selection" from context menu. If you press reset buttons after successful starting of EMAC, next init is OK ? May hack a existing Linux with binary code in order to repeat init EMAC until not OK...
