Quartus 14.0 Clock generation

May be problem is not in Quartus clocks ?

My Altera CV Board have 2 Ethernet MACs:

10/100/1000 Ethernet (HPS EMAC) with RGMII connection to PHY at 250 Mbps;

10/100 Ethernet (FPGA internal MAC) with MII connection using 25 Mbps.

You are used first internal HPS EMAC without internal FPGA-core ? Second "soft"-MAC is meaningless ?

HPS EMAC must be worked without FPGA configuration, for example, download .rbf from Internet on Pover On and "bare" FPGA, save it to flash and configure FPGA with it after... Clock 250 to Ethernet system must be given independently from FPGA!

Problem may be in PHY or ways to it in board.

Pinging from board to host (from host) is normal ?

May be PHY "mirror" mode to return all sended from EMAC data back to.