Quartus 14.0 Clock generation

The board is self made.

WE boot via QSPI (NOR chip EPCQ256)

With Quartus 13.1 it's not possible to use 27MHz. Maybe it is, but then you have to manually adjust the PLL_config.h file.

On rev0 we are using a 5CSEBA5U23I7N with 27MHZ. Because back then, we had only quartus 13.1. we fixed the 27MHz to 25MHz.

After fixing the Clock, the board worked. we used nfs to boot linux.

On rev1 we are using a 5CSEBA4U23C7N with 27MHZ. Because now quartus 14.0 allows you to change the PLL settings. we can enter UBOOT, but running NFS (stable) is not possible. I don't know why. The only thing I can think of is the PLL not locking or the 249.75 MHZ is not good enough.

settings are

Osc1_clk = 27MHz

sclk_out = 27MHz

qspi_clk = 108MHz

mpu_clk = 216 MHz

EMAC = 249.75MHZ