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Niko3's avatar
Niko3
Icon for Occasional Contributor rankOccasional Contributor
2 years ago
Solved

programming successful but no function of CPLD

Hi, I am quite new with CPLD design and hope to get help here. For test purposes and learning I made a simple schematic with an external clock of 1 kHz, a 4bit counter (74161) and a BCD to 7 segment...
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Programmable Logic Device
  • FvM's avatar
    FvM
    2 years ago

    Hi,
    which series resistor value? Clock edge may be too slow and cause multiple transitions. As you say it's a self designed board, insufficient power supply bypassing and ground bounce can cause irregular CPLD behaviour.

Niko3's avatar
Niko3
Icon for Occasional Contributor rankOccasional Contributor
2 years ago

I didn't write code. I used the block editor to design the schematic, see attachment (for EPM240).

I also made a simulation which showed correct waveforms.

FvM's avatar
FvM
Icon for Super Contributor rankSuper Contributor
2 years ago
Hi,
how do you observe the counter output? What's the 1 kHz external clock source, sure it's suited as CPLD clock?
  • Niko3's avatar
    Niko3
    Icon for Occasional Contributor rankOccasional Contributor
    2 years ago

    I use a DSO/state analyzer. It has a 5V 1 kHz clock output. The 5V output is scaled down to 2.8V with a serial resistor and a zener diode.

    Five channels of the state analyzer show the clock input and the 4 counter outputs which are connected to pins of the CPLD.

    • FvM's avatar
      FvM
      Icon for Super Contributor rankSuper Contributor
      2 years ago

      Hi,
      which series resistor value? Clock edge may be too slow and cause multiple transitions. As you say it's a self designed board, insufficient power supply bypassing and ground bounce can cause irregular CPLD behaviour.

      • Niko3's avatar
        Niko3
        Icon for Occasional Contributor rankOccasional Contributor
        2 years ago

        Thank you FvM for your tips.

        It really was a too slow clock slope. After many tests with varying conditions I had a look on the clock slope with high time resolution, see the attachment. The yellow track is the rising edge of original 1 kHz clock and the red one is after an inverter. With the improved slope my circuit works fine.