Forum Discussion
Honored ContributorProblem with Always block
I have an Always block that is supposed to run when variable a assigned to 1. But it actually runs anytime when synthesising in Quartus. Can anyone help me resolve it? :confused:
module main;
bit a = 0;
always @ (a==1)
begin
// Run code
end
endmodule
10 Replies
Altera_ForumFirst of all i cant comment whether this is synthesizable because generally we write always @ (signal) or always @ (posedge clk or negedge rst) we dont check any value in the sensitivity list. I personally havnt seen such a code like what you have written. Is it synthesizable ? Did the tool throw an error ?
That being said lets assume that its synthesizable then the question arises that what kind of logic you want. If you want a combi logic and if this code is synthesizable i guess it can work..but if you want a sequential logic i guess i wont work and the tool must throw an error. Now again if this is synthesizable it will be synthesized irrespective of the value. But i guess you should change the coding style. Lets say you want a block of code to be executed only if a==1'b1. You can write like this always @ * for combi or always @ (posedge sys_clk or negedge rst) Note: if reset is synchronous then only always @ (posedge clk) for sequential logic and then give highest priority to "a" like always @* begin if (a==1'b1) //code end yes the always block will be synthesized but you will see effects in simulation. I really have no idea for always @ (a==1). GOOD LUCK- Altera_Forum
I changed the always block, but it always run the code inside whatever the variable a is. :p
always @* begin if (a==1'b1) //code end - Altera_Forum
Yes it will offcourse, i did mention it in my previous post.
Look "a" has to be some parameter or a static signal. You cannot control synthesis of a logic based on a variable which is either in the portlist or defined as a signal. Now if you have "a" as a parameter then you can do something like this parameter a = 1'b1 generate if (a==1'b1) begin always @ * begin //code end end but i dont think if a is a signal then you can control synthesis of the code. - Altera_Forum
There's a simple answer to this post.
sensitivity lists in always blocks except posedge or negedge are ignored in synthesis. Sensitivity lists matters in smulation, synthesis results are identical to always @ * Why is it so? Level sensitive always blocks are describing combinational logic. The synthesized logic equations are combinations of input terms, they are assigned unconditionally, not depending on any events. Functional simulation is working different, interpreting the code line by line. Sensitivity lists are used to save simulation time, evaluating only the part of the code that is expected to have changed output. - Altera_Forum
Thank you all.
- Altera_Forum
I am wondering if there is a way to intentionally send a signal to execute a logic when we need rather than using a clock signal. :rolleyes:
- Altera_Forum
Look you should keep in mind that a hardware is static and concurrent.
You cant instantiate a logic dependent on a variable signal, that not the correct way. Think over your logic , learn about generate block. Good luck - Altera_Forum
Thanks for your advice. :)
- Altera_Forum
Can anyone help me resolve this error:
genvar j; generate task gen; for (j=1; j<=10; j++) begin // end endtask endgenerateError : value must not be assigned to nonvariable "j" - Altera_Forum
Your usage of the keywords task/endtask doesn't comply with the Verilog generate syntax, I think. Try with the syntax specified in the Verilog specification.
