Problem with Always block

Yes it will offcourse, i did mention it in my previous post.

Look "a" has to be some parameter or a static signal.

You cannot control synthesis of a logic based on a variable which is either in the portlist or defined as a signal.

Now if you have "a" as a parameter then you can do something like this

parameter a = 1'b1

generate

if (a==1'b1) begin

always @ *

begin

//code

end

end

but i dont think if a is a signal then you can control synthesis of the code.