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Altera_Forum's avatar
Altera_Forum
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14 years ago

Problem with Always block

I have an Always block that is supposed to run when variable a assigned to 1. But it actually runs anytime when synthesising in Quartus. Can anyone help me resolve it? :confused: module mai...
Altera_Forum's avatar
Altera_Forum
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13 years ago

Your usage of the keywords task/endtask doesn't comply with the Verilog generate syntax, I think. Try with the syntax specified in the Verilog specification.