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Altera_Forum's avatar
Altera_Forum
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14 years ago

Problem with Always block

I have an Always block that is supposed to run when variable a assigned to 1. But it actually runs anytime when synthesising in Quartus. Can anyone help me resolve it? :confused: module mai...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

Look you should keep in mind that a hardware is static and concurrent.

You cant instantiate a logic dependent on a variable signal, that not the correct way. Think over your logic , learn about generate block.

Good luck