Problem with Always block

First of all i cant comment whether this is synthesizable because generally we write always @ (signal) or always @ (posedge clk or negedge rst) we dont check any value in the sensitivity list. I personally havnt seen such a code like what you have written. Is it synthesizable ? Did the tool throw an error ?

That being said lets assume that its synthesizable then the question arises that what kind of logic you want. If you want a combi logic and if this code is synthesizable i guess it can work..but if you want a sequential logic i guess i wont work and the tool must throw an error.

Now again if this is synthesizable it will be synthesized irrespective of the value.

But i guess you should change the coding style.

Lets say you want a block of code to be executed only if a==1'b1.

You can write like this

always @ * for combi or always @ (posedge sys_clk or negedge rst)

Note: if reset is synchronous then only always @ (posedge clk) for sequential logic and then give highest priority to "a" like

always @*

begin

if (a==1'b1)

//code

end

yes the always block will be synthesized but you will see effects in simulation. I really have no idea for always @ (a==1).

GOOD LUCK