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Altera_Forum
Honored Contributor
14 years agoProblem with Always block
I have an Always block that is supposed to run when variable a assigned to 1. But it actually runs anytime when synthesising in Quartus. Can anyone help me resolve it? :confused:
module mai...
Altera_Forum
Honored Contributor
14 years agoThere's a simple answer to this post.
sensitivity lists in always blocks except posedge or negedge are ignored in synthesis. Sensitivity lists matters in smulation, synthesis results are identical to always @ * Why is it so? Level sensitive always blocks are describing combinational logic. The synthesized logic equations are combinations of input terms, they are assigned unconditionally, not depending on any events. Functional simulation is working different, interpreting the code line by line. Sensitivity lists are used to save simulation time, evaluating only the part of the code that is expected to have changed output.