Forum Discussion
Honored ContributorProblem using VHDL from a project lower in the heirarchy in an upper level
I created a very simple dual edge detector using D flip flops and a few logic gates. I created this using Megafunctions LPM_DFF, LPM_XOR, LPM_INV, and LPM_AND symbols. This project compiles and creates the VHDL and symbol without issue. When I try to use the symbol in a project, I am unable to compile the project and get the following error.
Error (10481): VHDL Use Clause error at lpm_dff_0.vhd(28): design library "work" does not contain primary unit "lpm_components" Error (10800): VHDL error at lpm_dff_0.vhd(28): selected name in use clause is not an expanded name Can help with why this rather straight forward application using only basic Quartus components would give this error? Are there some settings in generating the VHDL that are not correct? I have not changed anything and tried reinstalling. Any help would be greatly appreciated.14 Replies
Altera_ForumI opened up PLD_Proxy, and although you have a top-level BSF, and what looks like a generated top-level VHDL file, I do not see a testbench file, eg., PLD_Proxy_tb.vhd.
Without that file, you're not going to get very far with simulation. I'd recommend taking the time now to create a basic testbench containing a clock generator, and a process that drives valid signals onto the input ports. At that point you will be able to see whether the output ports are all driven to valid values. Then you can start to add test sequences. The testbench I posted should be enough to get you started. Cheers, Dave- Altera_Forum
Dave I didn't see your previous reply before sending out my previous one. First, let me say thanks for your patience. I spent 3 years working with Quartus on multiple projects, but the last one was 5 years ago. Things have certainly changed a bit. To answer you question, only needed the equivalent of three clocks to test this circuit, so I just manually applied then using the same facility as force. Sorry if I was not clear enough in the past.
- Altera_Forum
I have traced my problem to connectivity problems where it say some of the Q output of my FF's are connected dangling logic. I have try renaming, renumbering, splitting, and finally connect my buses only by signal names. I have attached my BDF file is someone can look at it and see what my problem is, I would be eternally grateful.
- Altera_Forum--- Quote Start --- I am just manually setting the inputs and output in modelsim to do the simulation testing. --- Quote End --- Manually? How, using force statements, or using a top-level VHDL testbench. Its hard to help you if I have to guess. Just post your code, or some minimal code that demonstrates the error. The testbench that I referred you to probably has enough to get you started - try running it. Cheers, Dave
- Altera_Forum
I am just manually setting the inputs and output in modelsim to do the simulation testing.
- Altera_Forum--- Quote Start --- I am connecting the signal in the low level block to input and output pins. In the top-level architecture I am connecting the inputs and the outputs of the symbol to input and output pins. I am using ModelSim for the lower level module simulation and these lower level pins read as input and output. Any ideas? --- Quote End --- Do you have a testbench wrapped around these components that actually drives the signals though? For example, take a look at modelsim_example.zip in this thread: http://www.alteraforum.com/forum/showthread.php?t=32386 Cheers, Dave
- Altera_Forum
I am connecting the signal in the low level block to input and output pins. In the top-level architecture I am connecting the inputs and the outputs of the symbol to input and output pins. I am using ModelSim for the lower level module simulation and these lower level pins read as input and output. Any ideas?
- Altera_Forum--- Quote Start --- Thanks for you quick help. Your answer provided a key clue. I indeed had to use LP_FF. I verified this using the LPM_PACK file that that the Quartus generated VHDL said to add if you used the work declaration. Again thanks for the help. --- Quote End --- You're welcome. --- Quote Start --- I still have one remaining problem that you might be able to shed some light on. When I simulate or compile the lower level block everything is find. When I insert this block in a higher level design and try to compile, I get an error saying all my inputs are not driving logic. All I did was connect input and out pins to the symbol, which compiled and simulated without problems. Any advice?? --- Quote End --- In your top-level design, are you connecting the ports on your component to signals declared in the top-level architecture, or to ports in the top-level architecture? If you are only connecting to signals, and those signals come from "nowhere", then that would be the source of your problem. In a simulation, you would see those signals as RED in the waveform viewer if they are not being driven by something. That's just a guess though ... do you have a working simulation with testbench? Cheers, Dave
- Altera_Forum
Thanks for you quick help. Your answer provided a key clue. I indeed had to use LP_FF. I verified this using the LPM_PACK file that that the Quartus generated VHDL said to add if you used the work declaration. Again thanks for the help.
I still have one remaining problem that you might be able to shed some light on. When I simulate or compile the lower level block everything is find. When I insert this block in a higher level design and try to compile, I get an error saying all my inputs are not driving logic. All I did was connect input and out pins to the symbol, which compiled and simulated without problems. Any advice?? - Altera_Forum
Are you sure you have copied the code correctly? According to:
http://www.altera.com/support/examples/vhdl/v_testdff.html The LPM component is LPM_FF, not LPM_DFF. A search in my 11.1sp1 installation shows the LPM component (C:\software\altera\11.1sp1\quartus\eda\sim_lib\ 220pack.vhd):
The comments in the example code regarding third party tools are incorrect. All tools can use the LPM library. You just need to create the LPM library, or map it to the work library. For example, in Modelsim vlib lpm vmap lpm [pwd]/lpm or vlib work vmap lpm [pwd]/work and then compile the components into that library vcom -work lpm 220pack.vhd vcom -work lpm 220model.vhd Modelsim-ASE already has this library configured with the source built into it. Cheers, Davecomponent LPM_FF generic(LPM_WIDTH : natural; -- MUST be greater than 0 LPM_AVALUE : string := "UNUSED"; LPM_SVALUE : string := "UNUSED"; LPM_PVALUE : string := "UNUSED"; LPM_FFTYPE: string := "DFF"; LPM_TYPE: string := L_FF; LPM_HINT : string := "UNUSED"); port (DATA : in std_logic_vector(LPM_WIDTH-1 downto 0) := (OTHERS => '1'); CLOCK : in std_logic; ENABLE : in std_logic := '1'; SLOAD : in std_logic := '0'; SCLR : in std_logic := '0'; SSET : in std_logic := '0'; ALOAD : in std_logic := '0'; ACLR : in std_logic := '0'; ASET : in std_logic := '0'; Q : out std_logic_vector(LPM_WIDTH-1 downto 0)); end component;
