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Thanks for you quick help. Your answer provided a key clue. I indeed had to use LP_FF. I verified this using the LPM_PACK file that that the Quartus generated VHDL said to add if you used the work declaration. Again thanks for the help.
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You're welcome.
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I still have one remaining problem that you might be able to shed some light on. When I simulate or compile the lower level block everything is find. When I insert this block in a higher level design and try to compile, I get an error saying all my inputs are not driving logic. All I did was connect input and out pins to the symbol, which compiled and simulated without problems. Any advice??
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In your top-level design, are you connecting the ports on your component to signals declared in the top-level architecture, or to ports in the top-level architecture?
If you are only connecting to signals, and those signals come from "nowhere", then that would be the source of your problem. In a simulation, you would see those signals as RED in the waveform viewer if they are not being driven by something.
That's just a guess though ... do you have a working simulation with testbench?
Cheers,
Dave
Honored Contributor
