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Altera_Forum
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13 years ago

Problem using VHDL from a project lower in the heirarchy in an upper level

I created a very simple dual edge detector using D flip flops and a few logic gates. I created this using Megafunctions LPM_DFF, LPM_XOR, LPM_INV, and LPM_AND symbols. This project compiles and cre...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

Dave I didn't see your previous reply before sending out my previous one. First, let me say thanks for your patience. I spent 3 years working with Quartus on multiple projects, but the last one was 5 years ago. Things have certainly changed a bit. To answer you question, only needed the equivalent of three clocks to test this circuit, so I just manually applied then using the same facility as force. Sorry if I was not clear enough in the past.