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Altera_Forum
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13 years ago

Problem using VHDL from a project lower in the heirarchy in an upper level

I created a very simple dual edge detector using D flip flops and a few logic gates. I created this using Megafunctions LPM_DFF, LPM_XOR, LPM_INV, and LPM_AND symbols. This project compiles and cre...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

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I am just manually setting the inputs and output in modelsim to do the simulation testing.

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Manually? How, using force statements, or using a top-level VHDL testbench.

Its hard to help you if I have to guess. Just post your code, or some minimal code that demonstrates the error.

The testbench that I referred you to probably has enough to get you started - try running it.

Cheers,

Dave