Problem using VHDL from a project lower in the heirarchy in an upper level

Thanks for you quick help. Your answer provided a key clue. I indeed had to use LP_FF. I verified this using the LPM_PACK file that that the Quartus generated VHDL said to add if you used the work declaration. Again thanks for the help.

I still have one remaining problem that you might be able to shed some light on. When I simulate or compile the lower level block everything is find. When I insert this block in a higher level design and try to compile, I get an error saying all my inputs are not driving logic. All I did was connect input and out pins to the symbol, which compiled and simulated without problems. Any advice??