Problem using VHDL from a project lower in the heirarchy in an upper level

I opened up PLD_Proxy, and although you have a top-level BSF, and what looks like a generated top-level VHDL file, I do not see a testbench file, eg., PLD_Proxy_tb.vhd.

Without that file, you're not going to get very far with simulation. I'd recommend taking the time now to create a basic testbench containing a clock generator, and a process that drives valid signals onto the input ports. At that point you will be able to see whether the output ports are all driven to valid values. Then you can start to add test sequences. The testbench I posted should be enough to get you started.

Cheers,

Dave