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Altera_Forum
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13 years ago

Problem using VHDL from a project lower in the heirarchy in an upper level

I created a very simple dual edge detector using D flip flops and a few logic gates. I created this using Megafunctions LPM_DFF, LPM_XOR, LPM_INV, and LPM_AND symbols. This project compiles and cre...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

I have traced my problem to connectivity problems where it say some of the Q output of my FF's are connected dangling logic. I have try renaming, renumbering, splitting, and finally connect my buses only by signal names. I have attached my BDF file is someone can look at it and see what my problem is, I would be eternally grateful.