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Altera_Forum
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13 years ago

Problem using VHDL from a project lower in the heirarchy in an upper level

I created a very simple dual edge detector using D flip flops and a few logic gates. I created this using Megafunctions LPM_DFF, LPM_XOR, LPM_INV, and LPM_AND symbols. This project compiles and cre...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

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I am connecting the signal in the low level block to input and output pins. In the top-level architecture I am connecting the inputs and the outputs of the symbol to input and output pins. I am using ModelSim for the lower level module simulation and these lower level pins read as input and output. Any ideas?

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Do you have a testbench wrapped around these components that actually drives the signals though?

For example, take a look at modelsim_example.zip in this thread:

http://www.alteraforum.com/forum/showthread.php?t=32386

Cheers,

Dave