Problem to simulate an entity in VHDL

Good afternoon colleagues,

I write to you as I have had a problem with the Simuation Waveform Editor of Quartus Prime Lite Edition. I am beginner in programming with this environment and I wanted to do the same thing as the guy in this short youtube tutorial: https://www.youtube.com/watch?v=1W6Aw6sZCjo&list=PLc3Oyld0v-1i4rhkFrwxb5GSfIoAQcYuE&index=4

The code I have written for this entity is the followin one and it compiles well:

library IEEE;
use IEEE.std_logic_1164.all;

entity prueba is 
   port (
    A: in std_logic;
    B: in std_logic;
    Y: out std_logic
   );
end entity;

architecture dataflow of prueba is
begin 
	Y<= A xor B;
end architecture;

What I wanted to do is to test the code with the University Program VWF and I did the same steps as the guy in the video. The problem appears when I Run the simulation and I get the following error message:

**** Running the ModelSim simulation ****

c:/intelfpga/23.1std/questa_fse/win64//vsim -c -do prueba.do

** Fatal: Failed to initialize licensing environment. License environment not set correctly.

Unable to checkout a license. Vsim is closing.

** Error: Invalid license environment. Application closing.

Error.

I really don't know what could be happening. I would appreciate if you can help me