Problem in compiling verilog code for EMP7064

The warnings indicate no timing constraints. You didn't add your .sdc files in the timing analyzer settings (they don't appear in the .qsf file). As for the functionality, what is the error/failure you are seeing?

.sdc files define timing constraints for your design to guide the Fitter during place and route. Your design may be failing timing, which might explain why it's not working. Take a look at the appropriate timing analyzer user guide here:

https://www.intel.com/content/www/us/en/support/programmable/support-resources/design-software/user-guides.html

Also, your flipflop design is not the proper implementation of a register so they are getting implemented as latches, which can also cause timing issues. See the Design Recommendations user guide at that same link for recommendations on how to properly code for registers.

From your flip flop design shown in the RTL viewer in the Screenshot_FF.jpg, the input (D) of the flip flop needs to connect to an input port or output of another flip flop in order to get timing analysis. It should not connect to a logic “1” otherwise no timing analysis can be performed.
Here is an example of the SDC file. You need to get the measured (max & min) input delay and output delay to set their values inside the SDC file to meet the timing requirements and constrain all paths. After that, you need to add the SDC file to the design. For other warnings, you may right click it > help to see its details.

Another suggestion is, you may use the built-in PLL (Phase-Locked Loop) function to create clock, it is much easier and organized. Then, instantiate the PLL in your top level module.

Arjun,

Is the suggestion above helpful?

Let me know any update on this

Hi,

Thank you for your response but I have no idea what any of this is. No one in my company knows anything about CPLD or Verilog. We wrote this code on Atmel with the help of youtube and other websites. We have floated a contract for this on Upwork and only when it is resolved I will be in a position to let you know if this worked or not.

Arjun,

Understood. Since you are gonna take sometime to work on this. I will put this to close pending and you may reopen and create new case query for assistance.