Problem in compiling verilog code for EMP7064

.sdc files define timing constraints for your design to guide the Fitter during place and route. Your design may be failing timing, which might explain why it's not working. Take a look at the appropriate timing analyzer user guide here:

https://www.intel.com/content/www/us/en/support/programmable/support-resources/design-software/user-guides.html

Also, your flipflop design is not the proper implementation of a register so they are getting implemented as latches, which can also cause timing issues. See the Design Recommendations user guide at that same link for recommendations on how to properly code for registers.