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ArjunGoel's avatar
ArjunGoel
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3 years ago

Problem in compiling verilog code for EMP7064

Hello, We have a verilog code which we build on Atmel ProChip Version 5.0 for ATF1504AS (5V and 44pin TQFP). Same is attached as "Atmel.zip". The output file is a .jed and we were of the opinio...
sstrell's avatar
sstrell
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3 years ago

The warnings indicate no timing constraints. You didn't add your .sdc files in the timing analyzer settings (they don't appear in the .qsf file). As for the functionality, what is the error/failure you are seeing?

  • ArjunGoel's avatar
    ArjunGoel
    Icon for New Contributor rankNew Contributor
    3 years ago

    Hello,

    The function of this code is to generate deadtime between PWM pulses. The error we face is that duty cycle of the PWM signal has changed.

    The output of Quartus is a .pof file and the output of ProChip (from Microchip/Atmel) is a .jed file. We have a tool to convert a .pof file to a .jed file. We have used this tool and converted the .pof file, which is giving issues in the Intel/Altera CPLD, to a .jed file for Microchip/Atmel CPLD and it works perfectly.

    We have no idea what a .sdc file is and how to generate one. Is it possible to connect with you via Upwork or anyother platform so that you can help us get this code working?