Problem in compiling verilog code for EMP7064

From your flip flop design shown in the RTL viewer in the Screenshot_FF.jpg, the input (D) of the flip flop needs to connect to an input port or output of another flip flop in order to get timing analysis. It should not connect to a logic “1” otherwise no timing analysis can be performed.
Here is an example of the SDC file. You need to get the measured (max & min) input delay and output delay to set their values inside the SDC file to meet the timing requirements and constrain all paths. After that, you need to add the SDC file to the design. For other warnings, you may right click it > help to see its details.

Another suggestion is, you may use the built-in PLL (Phase-Locked Loop) function to create clock, it is much easier and organized. Then, instantiate the PLL in your top level module.