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Altera_Forum's avatar
Altera_Forum
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14 years ago

Problem in ahdl-source

Hello all!

I want create component which holds vcc-state after than high state is on each input. Clr resets state.

I supposed that is a very simple.

My idea is using dffe primitive with: clk = Inp, d = vcc, clrn = not(Rst).

My code for 32 inputs is below:

CODE BEGIN

-- Prototype function dffe

--FUNCTION DFFE (D, CLK, CLRN, PRN, ENA)

--RETURNS (Q);

PARAMETERS

(

Width = 32

);

SUBDESIGN holdmax

(

clk : INPUT; -- clock

Ena : INPUT; -- enable

Rst : INPUT; -- reset by "1"

I[Width-1..0]: INPUT; -- input data bus

O[Width-1..0]: OUTPUT; -- quit

)

VARIABLE

tapes[Width-1..0] : NODE;

BEGIN

FOR k IN 0 TO (Width-1) GENERATE

tapes[k] = dffe(vcc, I[k], not(Rst), vcc, Ena);

END GENERATE;

O[] = tapes[];

END;

CODE END

But I have problems with my code:(

This code is compiled in Quartus 9.1 correctly. Another situation is in Max2Plus!

I have warning "Ignored unnecessary INPUT pin 'Clk'" and signal Clk is not used!(?)

I need code which can be compiled correctly in either program.

Where is my problem? Is it my bad code?

Thanks all!

4 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    14 years ago

    If I were you, I would rewrite your code in VHDL or Verilog an compile it under Quartus II.

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    14 years ago

    2All:

    I solved my problem.

    2celsung: (http://www.alteraforum.com/forum/member.php?u=5333)

    Thank you for answer!

    It is a good decision for me. But I expain: Now I see that Clk signal is ignored in Quartus too. I did some mistakes when used Max2Plus:(

    Compiled results are equal in either software Max2Plus and Quartus.

    If you want you can rewrite my code. Now I use "xport.exe" utility (from Xilinx software) for conversion ahdl to verilog (or vhdl).

    I want to compare youre code and my verilog code which was translated by "xport" utility (If you want of cource:))
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    14 years ago

    library ieee;

    use ieee.std_logic_1164.all;

    entity eugen is

    port (

    clk : in std_logic;

    clrn : in std_logic;

    o : out std_logic_vector(31 downto 0)

    );

    end eugen;

    architecture eugen_RTL of eugen is

    begin

    process (clk, clrn)

    begin

    if (clrn = '0') then

    o <= (others => '0');

    elsif rising_edge(clk) then

    o <= (others => '1');

    end if;

    end process;

    end eugen_RTL;