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Altera_Forum's avatar
Altera_Forum
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15 years ago

Problem in ahdl-source

Hello all! I want create component which holds vcc-state after than high state is on each input. Clr resets state. I supposed that is a very simple. My idea is using dffe primitive with: clk =...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

library ieee;

use ieee.std_logic_1164.all;

entity eugen is

port (

clk : in std_logic;

clrn : in std_logic;

o : out std_logic_vector(31 downto 0)

);

end eugen;

architecture eugen_RTL of eugen is

begin

process (clk, clrn)

begin

if (clrn = '0') then

o <= (others => '0');

elsif rising_edge(clk) then

o <= (others => '1');

end if;

end process;

end eugen_RTL;