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Altera_Forum
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14 years ago

Problem in ahdl-source

Hello all! I want create component which holds vcc-state after than high state is on each input. Clr resets state. I supposed that is a very simple. My idea is using dffe primitive with: clk =...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

If I were you, I would rewrite your code in VHDL or Verilog an compile it under Quartus II.