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Honored Contributor
Honored ContributorProblem in ahdl-source
Hello all! I want create component which holds vcc-state after than high state is on each input. Clr resets state. I supposed that is a very simple. My idea is using dffe primitive with: clk =...
Altera_ForumHonored Contributor
Honored ContributorIf I were you, I would rewrite your code in VHDL or Verilog an compile it under Quartus II.
