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Altera_Forum's avatar
Altera_Forum
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15 years ago

Problem in ahdl-source

Hello all! I want create component which holds vcc-state after than high state is on each input. Clr resets state. I supposed that is a very simple. My idea is using dffe primitive with: clk =...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

2All:

I solved my problem.

2celsung: (http://www.alteraforum.com/forum/member.php?u=5333)

Thank you for answer!

It is a good decision for me. But I expain: Now I see that Clk signal is ignored in Quartus too. I did some mistakes when used Max2Plus:(

Compiled results are equal in either software Max2Plus and Quartus.

If you want you can rewrite my code. Now I use "xport.exe" utility (from Xilinx software) for conversion ahdl to verilog (or vhdl).

I want to compare youre code and my verilog code which was translated by "xport" utility (If you want of cource:))