Forum Discussion
Altera_Forum
Honored Contributor
Honored ContributorProblem for simulate PLL with Modelsim-Altera
Problem of simulations
Since block Diagram.bdf, I use Run gate-level simulation automatically from EDA simulat Tool of quartusII.7.2 Web Edition I can stimulate the PLL (Altera_mf, Altpll) but I do not know how to see the simulation of all the signals of all other entitys? Only I see the outputs of TOP-Level and the signals of the PLL. In WORK of Modelsim-Altera6.1, I see the components: Altll, Samsertop (top-level), Samsertop_vhd_vec_tst, but not the other components. In the tab Sim, I see i1, inst, but not inst1!! Is it normal? which are the steps, I must to do? For put a component in Block Diagram.bdf, I make a right click in .bdf = > insert = > symbol. Then I wanted to stimulate directly with Modelsim. I make: FILE = > New = > Project FILE = > New = > Library = > Work FILE = > Add to projet_ existing files Then I compile = > compile order: Horloge.vhd ( altPll ) 0, Ram.vhd 1, TopSamser. vhd ( top-level) 2, BenchSamser ( testBench ) 3 Then, I start simulatioon and I select the testBench (BenchSamser) . There, I cannot stimulate the PLL (Altera_mf, Altpll). My vectors of simulation arrive in altpll but are not stimulate from the outputs. I have no error message. I think, that it does not compile Altpll. what must I do ? https://www.alteraforum.com/forum/attachment.php?attachmentid=11067 Replies
Altera_Forumthank you
exactly. i works.- Altera_Forum
From the Menu Simulate->Start Simulation
Select your design unit that you want to simulate and resolution from the pull down called "resolution". Obvious once you've found it! Not Obvious if you haven't! Hope this helps - Altera_Forum--- Quote Start --- If you observe no output from the PLL without an error message, it's most likely due to the default resolution = ns vsim setting. It must be changed to resolution = ps to simulate a PLL. --- Quote End --- hello, please can you tell me how can i change the resolution of simulator modelsim because whe i simulated the ALTPLL i met a problem and a warning was appeared "time unit 'ps' is less than the simulator resolution(1ns). thank you an advance
- Altera_Forum
My block diagram is an example but it is simulate. I always do not see instanciations. I want to know if it is normal.
- Altera_Forum
I didn't ever simulate BDF designs, also your design hierarchy isn't completely clear to me. But you surely can find all signals involved with your design by climbing down the hierarchy. At worst case, you'll have some difficulties to identify the entity names. But they should basically correspond to the hierarchy displayed in Quartus RTL viewer.
- Altera_Forum
https://www.alteraforum.com/forum/attachment.php?attachmentid=1110 Thank you very much for your answer.
It is exact with a resolution of ps, the simulation is now correct. Could you say to me? If for a simulation with Run gate-level simulation automatically from EDA simulat Tool of quartusII, if it is normal that I see only the instanciation Inst and in the library Word of Modelsim I see only Altpll, Horloge, Samsertop and not Benchanaload and Etpot corresponding to the block diagram.bdf which I joined previously https://www.alteraforum.com/forum/attachment.php?attachmentid=1110 . - Altera_Forum--- Quote Start --- My vectors of simulation arrive in altpll but are not stimulate from the outputs. I have no error message. --- Quote End --- If you observe no output from the PLL without an error message, it's most likely due to the default resolution = ns vsim setting. It must be changed to resolution = ps to simulate a PLL.
