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Altera_Forum
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16 years ago

Problem for simulate PLL with Modelsim-Altera

Problem of simulations Since block Diagram.bdf, I use Run gate-level simulation automatically from EDA simulat Tool of quartusII.7.2 Web Edition I can stimulate the PLL (Altera_mf, Altpll) ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

I didn't ever simulate BDF designs, also your design hierarchy isn't completely clear to me. But you surely can find all signals involved with your design by climbing down the hierarchy. At worst case, you'll have some difficulties to identify the entity names. But they should basically correspond to the hierarchy displayed in Quartus RTL viewer.