Forum Discussion

SK_VA's avatar
SK_VA
Icon for Occasional Contributor rankOccasional Contributor
6 years ago

Pre emphasis and Equalization in Stratix 10

Hi,

I am new to transceiver training toolkit.I did the Intel training for transceiver training toolkit. Even though the training explains about different PMA settings options available in toolkit,it doesn't give a clear view on how to decide and set values for VOD,pre emphasis and equalisation settings.

I would like to know if there are good references that explain the PMA settings and its impact on BER.

15 Replies

  • CheepinC_altera's avatar
    CheepinC_altera
    Icon for Regular Contributor rankRegular Contributor
    6 years ago

    Hi,

    As I understand it, you have some inquiries related to the explanation references for S10 PMA settings ie VOD, pre-emphasis and equalization. For your information, based on my understanding, there is no specific documentation on this. However, on the high level, the following might be helpful to you:

    1. VOD would affect the eye opening of the TX output voltage swing. The high the VOD value, the larger the voltage swing.

    2. pre-emphasis would affect the rising and falling edge. You would need to tune to the optimal settings which can give you optimal eye.

    3. RX equalization - generally these parameters would help to boost the eye of the received signals

    Specific to S10 TX PMA settings, you may refer to the following estimator which will provide you a better graphical illustration on the VOD and pre-emphasis settings.

    https://www.intel.com/content/dam/altera-www/global/en_US/others/literature/hb/stratix-10/stratix10_htile_pre_emphasis_and_output_swing_estimator.xlsx

    Note that the required combination of PMA settings would be dependent on your board. You would need to tune the settings to achieve your target BER.

    Please let me know if there is any concern. Thank you.

    Best regards,

    Chee Pin

    • SK_VA's avatar
      SK_VA
      Icon for Occasional Contributor rankOccasional Contributor
      6 years ago

      Hi,

      Can I use an example design targeting H Tile stratix 10 device for L Tile Stratix device.

      Regards,

      Sanju

  • CheepinC_altera's avatar
    CheepinC_altera
    Icon for Regular Contributor rankRegular Contributor
    6 years ago

    Hi Sanju,

    Regarding your latest inquiry on using H tile design for L Tile design, based on my understanding, you cannot directly use H tile for L Tile because they are different devices.

    As a workaround, you could refer to the H tile design, and then create a new design from scratch for the L Tile.

    Another alternative to try out would be to change the device from H tile to L tile in design, and then perform IP auto-upgrade to see if it works. Note that if you may need to redo the pin assignments after changing to L tile device.

    Please let me know if there is any concern. Thank you.

    • SK_VA's avatar
      SK_VA
      Icon for Occasional Contributor rankOccasional Contributor
      6 years ago

      Hi,

      I am using the following example design;

      https://www.intel.com/content/dam/altera-www/global/en_US/uploads/d/d2/S10_SIBoard_UltraliteII_V2_8_Lanes_26G.zip

      This design is targeted for 1SG280HU2F50E2VG (H-Tile device). But I am compiling the design for 1SG280LN2F43E2VG(L-Tile device)

      As my target device is different tile and package,I have made necessary changes in pin mapping.

      Analysis and Synthesis passes. But fitter fails with error :

      Error(11653): Output port "PCIE_SW_DONE[0]" of "HSSI_CR2_PMA_TX_CGB" cannot connect to HSSI port "PMA_PCIE_SW_DONE[0]" of "HSSI_COMMON_PCS_PMA_INTERFACE" for atom "\Generate_Ultralite_II_Instances:0:instx|ultraliteii_txrx_module_inst|xcvr_txrx_inst|xcvr_txrx_inst|xcvr_native_s10_htile_0|g_xcvr_native_insts[1].ct2_xcvr_native_inst|inst_ct2_xcvr_channel_multi|gen_rev.ct2_xcvr_channel_inst|gen_ct1_hssi_common_pcs_pma_interface.inst_ct1_hssi_common_pcs_pma_interface".

  • CheepinC_altera's avatar
    CheepinC_altera
    Icon for Regular Contributor rankRegular Contributor
    6 years ago

    Hi,

    As I understand it, you seems to observe Fitter error when trying to port a S10 H-Tile device to L-Tile device. For your information, generally it is recommended for you to refer to the H-tile design and then create a fresh design in L-tile device to avoid any incompatibility issue.

    By looking merely looking at the current error, it is rather difficult to tell what might be wrong. If you would like to continue debugging on your existing design which was directly ported from S10 H-Tile, it would be great if you could start by trimming the design to only 1 XCVR channel. Then compile to see if it can pass Fitter. This would ease the debugging process.

    Please let me know if there is any concern. Thank you.

    Best regards,

    Chee Pin

    • SK_VA's avatar
      SK_VA
      Icon for Occasional Contributor rankOccasional Contributor
      6 years ago

      Hi ,

      I am able to run my transceiver example design with transceiver toolkit.

      I performed an auto sweep and eyeviewer on the transceiver links.

      I am able to see the BER 0 and best PMA settings in Transceiver link channel manager.But when I open the heat map window the eyediagram is just a small blue line at the center with eyewidth/height ratio 1.

      Please let me know what could be reasons for this?

      • SK_VA's avatar
        SK_VA
        Icon for Occasional Contributor rankOccasional Contributor
        6 years ago

        I could see in Strartix 10 device errata that "On-die instrumentation (ODI) (Eye-Q) is not available in Intel Stratix 10 devices that use the transceiver L-tile".

        Does this mean that eye diagram cannot be plotted for L tile strartix 10 devices?

        I am using 1SG280LN2F43E2VG (L- tile device) in my design.

  • CheepinC_altera's avatar
    CheepinC_altera
    Icon for Regular Contributor rankRegular Contributor
    6 years ago

    Hi,

    Regarding your observation with S10 L-Tile eye viewer, yes, you are right, the Eye viewer is not supported for S10 L-tile devices. As a workaround, in L-Tile devices, you may use the BER link test to check on the optimal PMA analog settings. Sorry for the inconvenience.

    Please let me know if there is any concern. Thank you.

    Best regards,

    Chee Pin

    • SK_VA's avatar
      SK_VA
      Icon for Occasional Contributor rankOccasional Contributor
      6 years ago

      Hi,

      Thanks .

      So I will be able to do only autosweep in the transceiver Toolkit for the links and find the optimal PMA settings for BER =0.

    • SK_VA's avatar
      SK_VA
      Icon for Occasional Contributor rankOccasional Contributor
      6 years ago

      Hi,

      I wanted to automate the toolkit tuning with tcl script. Please let me know how can I do this.

      Is there ways to save the steps done in GUI as tcl script.

      Every time I open the system console I need to create the transceiver Links.Is there ways to save transceiver link setup?

  • CheepinC_altera's avatar
    CheepinC_altera
    Icon for Regular Contributor rankRegular Contributor
    6 years ago

    Hi,

    Sorry for the delay. Regarding the automation, sorry as there seems to be no example of TCL script for S10 tuning automation. Generally we would make use of the auto-sweep and BER link test in the TTK to facilitate the tuning. Also, we are unable to save the steps done in GUI as TCL script. You would need to perform some manual work ie creating XCVR link setup before running the tuning. Sorry for the inconvenience.

    Best regards,

    Chee Pin

  • CheepinC_altera's avatar
    CheepinC_altera
    Icon for Regular Contributor rankRegular Contributor
    6 years ago

    Hi,

    Just would like to follow up with you if there is any further inquiry on this. Please let me know if there is any concern. Thank you.

    Best regards,

    Chee Pin

    • SK_VA's avatar
      SK_VA
      Icon for Occasional Contributor rankOccasional Contributor
      6 years ago

      Hi,

      Is there any user guidelines on setting TX and RX FIFO full and empty threshold values for stratix 10 native PHY IP?

  • CheepinC_altera's avatar
    CheepinC_altera
    Icon for Regular Contributor rankRegular Contributor
    6 years ago

    Hi,

    Regarding your latest inquiry on the guideline for FIFO threshold values, sorry as there is no specific guidelines on this. Generally the values will be dependent on user's design requirement. For your information, there are a number of protocol specific presets available in the Native PHY. You may try to select one of the preset which is closest to your target application and refer to the threshold values as a quick start.

    Please let me know if there is any concern. Thank you.

    Best regards,

    Chee Pin