Occasional Contributor
Regular ContributorHi Sanju,
Regarding your latest inquiry on using H tile design for L Tile design, based on my understanding, you cannot directly use H tile for L Tile because they are different devices.
As a workaround, you could refer to the H tile design, and then create a new design from scratch for the L Tile.
Another alternative to try out would be to change the device from H tile to L tile in design, and then perform IP auto-upgrade to see if it works. Note that if you may need to redo the pin assignments after changing to L tile device.
Please let me know if there is any concern. Thank you.
Occasional ContributorHi,
I am using the following example design;
https://www.intel.com/content/dam/altera-www/global/en_US/uploads/d/d2/S10_SIBoard_UltraliteII_V2_8_Lanes_26G.zip
This design is targeted for 1SG280HU2F50E2VG (H-Tile device). But I am compiling the design for 1SG280LN2F43E2VG(L-Tile device)
As my target device is different tile and package,I have made necessary changes in pin mapping.
Analysis and Synthesis passes. But fitter fails with error :
Error(11653): Output port "PCIE_SW_DONE[0]" of "HSSI_CR2_PMA_TX_CGB" cannot connect to HSSI port "PMA_PCIE_SW_DONE[0]" of "HSSI_COMMON_PCS_PMA_INTERFACE" for atom "\Generate_Ultralite_II_Instances:0:instx|ultraliteii_txrx_module_inst|xcvr_txrx_inst|xcvr_txrx_inst|xcvr_native_s10_htile_0|g_xcvr_native_insts[1].ct2_xcvr_native_inst|inst_ct2_xcvr_channel_multi|gen_rev.ct2_xcvr_channel_inst|gen_ct1_hssi_common_pcs_pma_interface.inst_ct1_hssi_common_pcs_pma_interface".
