PRBS transceiver

Assuming I understand you (though not sure about your setup and which ip you are referring to)

You can add prbs to your design in one single build and use a switch to select input.

here is example of 25 bits prbs:

process(reset, clk)
begin
if(reset = '1')then
   shift_reg <= '0'    & x"00F0F1";
elsif(rising_edge(clk))then
       shift_reg(1) <= shift_reg(25) xor shift_reg(22);
      shift_reg(25 downto 2) <= shift_reg(24 downto 1);
end if;
end process;

for your data you choose the required bits from shift_reg bits

Here's a document on how to generate arbitrary PRBS sequences;

http://www.ovro.caltech.edu/~dwh/correlator/pdf/lfsr_tutorial.pdf

I can post the code if you like.

When testing a transceiver, you want to generate the PRBS sequence multiple bits at a time in the FPGA fabric, and then send it to the transceiver for serialization. The 1-bit sequence on the transceiver lane will then be the PRBS sequence as indicated by Kaz's code.

Altera's pattern generator/checker cores have PRBS options. If you look at their code, you'll see they hard-code the PRBS parallel generation logic. In my code, you pass in a generator polynomial, and VHDL functions generate the underlying logic.

Cheers,

Dave

Hello :

Could you post your code as you mentioned.

thanks

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Could you post your code as you mentioned.

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Its right next to the PDF:

http://www.ovro.caltech.edu/~dwh/correlator/cobra_docs.html (http://www.ovro.caltech.edu/%7edwh/correlator/cobra_docs.html)

http://www.ovro.caltech.edu/~dwh/correlator/pdf/lfsr_tutorial_src.zip

Cheers,

Dave

Hi Dave

Transmitted PRBS sequence will be received at the Receiver end but how do we synchronize this sequence to the PRBS sequence generated at the receiver end and show that the BER is zero

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Transmitted PRBS sequence will be received at the Receiver end but how do we synchronize this sequence to the PRBS sequence generated at the receiver end and show that the BER is zero

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There's two ways:

1) You can receive a block of received bits, eg., 16-bits of the PRBS sequence, and use that as the seed to a local PRBS generator. The output of that local generator can then be XORed with the incoming stream.

Basically, you use the incoming PRBS stream to 'seed' your local generator, and then use your local generator to 'predict' what the next received pattern should be. The XOR of those patterns should be zero if they match.

You need a small control FSM to determine when to load the seed versus when to check the patterns and increment the BER counters.

This is how the Altera pattern generators/checkers work.

2) You can use the receiver pattern matching/alignment features.

I need to align multiple PRBS lanes. To do that, I use the pattern alignment features of the receiver, I use FIFOs to cross from the multiple receiver clock domains, and I use a local PRBS to track synchronization.

I can explain this second option in more detail if you need it.

Cheers,

Dave

hi Dave:

If you use the IP generated as a PRBS pattern mode datapath with external loopback connection using the megawizard (i.e Cy IV fig 1-74 transceiver arch spec) , do you need to take care of the synchronization/alignment manually or these megawizard generated blocks do everything for you except for connectivity to the pins.

thank you

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If you use the IP generated as a PRBS pattern mode datapath with external loopback connection using the megawizard (i.e Cy IV fig 1-74 transceiver arch spec) , do you need to take care of the synchronization/alignment manually or these megawizard generated blocks do everything for you except for connectivity to the pins.

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That is yet another PRBS pattern generator/checker. Altera have IP cores that you can use in the fabric too.

I haven't used these features of the transceivers, since they are basically hard-wired, i.e., if you select that feature in the transceiver IP block, you cannot actually use it for transmission or reception.

Create an instance of the ALTGX component with that option selected, and I'm sure there must be some status signals that indicate whether or not pattern errors are generated.

Personally I prefer implementing that checking logic in the fabric, as then I can transmit actual data as well.

The Altera PRBS generator/checker is described in (Ch 35 or 36)

http://www.altera.com/literature/ug/ug_embedded_ip.pdf

Cheers,

Dave

Hi Dave

I have downloaded the PRBS code from

http://www.ovro.caltech.edu/~dwh/cor...torial_src.zip (http://www.ovro.caltech.edu/%7edwh/correlator/pdf/lfsr_tutorial_src.zip)

Inside the src folder there is a module named lfsr.vhd

In that you are using if generate statement

Can i know what this infer in hardware does it infer a mux for

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d and data as shown below

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or will it select g1 or g2 for synthesis at run time and discards the other

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-- -----------------------------------------------------------

g1: if (INVERT) generate

d <= not seed;

data <= not q;

end generate;

g2: if (not INVERT) generate

d <= seed;

data <= q;

end generate;

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also you used the same approach for selecting Galois and Fibonacci

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Inside the src folder there is a module named lfsr.vhd

In that you are using if generate statement

Can i know what this infer in hardware does it infer a mux for or will it select g1 or g2 for synthesis at run time and discards the other

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Generate statements select the logic at the time of synthesis.

You can answer this question yourself by looking at the Quartus II synthesis results; look in the hierarchy display window and you'll see either g1 or g2, never both. Look in the RTL netlist view, and again, you'll see either g1 or g2.

Cheers,

Dave