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Inside the src folder there is a module named lfsr.vhd
In that you are using if generate statement
Can i know what this infer in hardware does it infer a mux for or will it select g1 or g2 for synthesis at run time and discards the other
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Generate statements select the logic at the time of
synthesis.
You can answer this question yourself by looking at the Quartus II synthesis results; look in the hierarchy display window and you'll see either g1 or g2, never both. Look in the RTL netlist view, and again, you'll see either g1 or g2.
Cheers,
Dave
Honored Contributor
