PRBS transceiver

Here's a document on how to generate arbitrary PRBS sequences;

http://www.ovro.caltech.edu/~dwh/correlator/pdf/lfsr_tutorial.pdf

I can post the code if you like.

When testing a transceiver, you want to generate the PRBS sequence multiple bits at a time in the FPGA fabric, and then send it to the transceiver for serialization. The 1-bit sequence on the transceiver lane will then be the PRBS sequence as indicated by Kaz's code.

Altera's pattern generator/checker cores have PRBS options. If you look at their code, you'll see they hard-code the PRBS parallel generation logic. In my code, you pass in a generator polynomial, and VHDL functions generate the underlying logic.

Cheers,

Dave