Porting of Ethernet Example Desgin from Arria 10 SX to Arria 10 GX Eval Board

I am currently trying to port the following Ethernet Example Design from the Arria 10 SX Eval Board to the Arria 10 GX Eval Board: https://www.intel.com/content/www/us/en/design-example/837384/arria-10-fpga-simple-socket-server-for-the-nios-v-m-processor-design-example.html

The Board change and IP Upgrade went fine, but when assigning the pins for the GX Board, I am running into multiple issues.

1. The clk_enet_fpga_p should be a 125 MHz clock. I tried assinging it to the CLK_125_P (Pin BD24) which is a 125 MHz clock (according to the Userguide of the GX Board, P. 75)
   1. This results in the following error
      

      >>> Why exactly can't I use this clock? I wasn't able to figure it out?

   2. I then switched to using a different clock. The clock REFCLK_FMCA_P (Pin AN8) works. However, the clock is too fast, so I tried adding an iopll and fpll (both tried individually).
      This resulted in the same error as above.
      >>> Why can't there be any PLL in the path?
      >>> Which clock should be used in the Arria 10 GX Eval Board for the Ethernet Example?
2. Later down the implementation, the design fails again, as apparently the I/O standard for the ENET_RX_N and ENET_RX_P signals is wrong.
   The userguide (P. 80) specifies them as LVDS:
   

   1. When set to LVDS, the following error happens:
      

      >>> Why is LVDS not allowed, eventhough it is stated as LVDS in the Userguide?

   2. When changed to the proposed "High-Speed Differential I/O" the following error occurs:

      

      >>> What is the correct standard?

I am using Quartus Prime Pro 24.3.0.