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LukiLeu's avatar
LukiLeu
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1 year ago

Porting of Ethernet Example Desgin from Arria 10 SX to Arria 10 GX Eval Board

I am currently trying to port the following Ethernet Example Design from the Arria 10 SX Eval Board to the Arria 10 GX Eval Board: https://www.intel.com/content/www/us/en/design-example/837384/arria-...
Board Debug
Configuration
Generic Io
LukiLeu's avatar
LukiLeu
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1 year ago

Hi Pavee

As I haven't received an answer in the case 06595988, I will post my follow up questions also here in this thread.

I just had a look at your provided qsf File. Are these pins really correct? When I look at the schematic, pin AU10 (for example) is routed to the FMCA connector instead of the Ethernet PHY.

The used schematic: https://www.intel.de/content/www/de/de/content-details/649803/arria-10-fpga-development-kit-dk-dev-10ax115s-a-board-schematic.html

Is it possible to obtain a full project instead of only the qsf File?