Port number limitation prevents my codes from compiling

I Looks like you have declared all 144 numbers to be transferred to the FPGA via 1Byte each as separate Inputs (144 x 8 = 1152 I/O pads + (assumed) some control, clock, ...).

If this is the real Hardware implementation you Need a FPGA with enough I/O Pins (I'm quite sure there is no such housing).

If the numbers are to be stored in internal Memory you normally have one 8Bit Port for the numbers and one 8 Bit port for the Memory address the number shall be stored at (2^8 = 255 "locations").

I think you need to re-check your code again...

How are you expecting the CPU to send these numbers? Your current code expects each number to have it's own individual input. Even if you did find an FPGA to accomodate this, how would you connect these to a CPU?

You need to think about the interface you intend to use between the CPU and FPGA and re-code accordingly. Maybe a single RS232 interface? or SPI? Ethernet? PCIe?

I suggest something simple.

Writing numbers to FPGA memory is a pretty simple task, but you wouldnt transfer the numbers directly to the FPGA pins.

Thank you Carlhermann

Your suggenstion that receive the numbers through address is good solution for me.

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Thank you Carlhermann

Your suggenstion that receive the numbers through address is good solution for me.

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How do you physically expect to connect your FPGA to the PC? Thru a serial connection (like an RS232 link), or etherNet, PCI bus, or PCIE bus? Or as just some bits that you toggle in a GPIO port on an expander card?

Each of these methods have very different levels of performance and complexity. Just wondering.

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I will use "Type A to B USB cable" contained in FPGA DE1-SoC to connect PC to FPGA.

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On the DE1-SOC the USB-B connection is for the Altera USB Blaster II programmer via JTAG. You really don't intend to use that, correct?

There is a mini USB B connection that is a USB serial to UART slave connection implemented via an FTDI FT232R USB-UART bridge. Is this what you intend to use?

If so, this will interface as a standard serial COM port on your PC, and connects to the HPS UART in the FPGA.

Thanks for your answer.

Actually, I don't have any knowledge about the connection(which connection I need to chhose), or how to transfer the data. I want to know the easiest way to transfer the data regardless of the connection. I will also search your suggestion "USB serial to UART slave connection".

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Thanks for your answer.

Actually, I don't have any knowledge about the connection(which connection I need to chhose), or how to transfer the data. I want to know the easiest way to transfer the data regardless of the connection. I will also search your suggestion "USB serial to UART slave connection".

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Well, I think that you need to figure out exactly what you want to do, and figure out an architecture that can do that. USB / serial UART communications has a significant performance limitation that may (or may not) be important for your application.

Or maybe in your DE1 SOC you want to have a more intelligent software subsystem that runs linux and interfaces over etherNet to transfer data from/to your host. Or maybe not even use the SOC CPU at all, and have your FPGA just be a dumb peripheral to an external PC via serial over USB.

SO I think you need to do a bunch of work to figure out what you want to do, at a high level, and design an architecture that can do it. Then start coding low level verilog ...