PLL problem using LVDS RX and TX pins on the same bank in a Cyclone V

Hello all,

I'm building a small loopback test setup, where I output data coming from a data pattern generated to a pair of LVDS signals (data & clock) and receive those same signals in another pair of differential signals (again data & clock). I'm using a Cyclone V SX, from the TerasIC SoCKit development board.

As far as I've tried, I can map the LVDS output pins to the respective LVDS TX ouput pins (A6 for data & C8 for clock), and the system fits. If I set specific pins for the LVDS RX pins as well (e.g. D11 for data & F13 for clock), the system no longer fits, indicating an error regarding the fractional PLL. It goes like this (only the red errors output by quartus):

Error (14566): Could not place 1 periphery component(s) due to conflicts with existing constraints (1 fractional PLL(s))
    Error (175001): Could not place fractional PLL, which is within ALTLVDS_TX lvds_test
            Error (177020): The PLL reference clock was not placed in a dedicated input pin that can reach the fractional PLL
Error (12289): An error occurred while applying the periphery constraints. Review the offending constraints and rerun the Fitter.

I have tried many things. I notice that if I assign either only the TX or the RX pins quartus fits well, but not with both at the same time. I believe it has something to do with the use of the same bank for both transmitting and receiving data via LVDS.

I can add that when I set only the TX pins and leave the RX pins unassigned (or the other way around), quartus fits the design but assigns the RX pins to some other differential pins that are not accessible due to how the SoCKit board is designed (only has access to differential TX and RX signals via the HSMC).

Is there any workaround for this problem?

Regards

EDIT: Both the RX and TX LVDS PLL clock resource are set to "Auto-select".