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Honored Contributor
Honored ContributorPLL problem using LVDS RX and TX pins on the same bank in a Cyclone V
Hello all, I'm building a small loopback test setup, where I output data coming from a data pattern generated to a pair of LVDS signals (data & clock) and receive those same signals in another ...
Altera_ForumHonored Contributor
Honored ContributorHi Finger-cutter
Quartus Software will automatically merge PLL when it has the chance. You might want to check if both TX and RX are sharing the same reset pin and also the same refclk pin. Given if the pll is in the same bank, then Quartus software will try to merge them.
