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Altera_Forum
Honored Contributor
Honored ContributorPLL problem using LVDS RX and TX pins on the same bank in a Cyclone V
Hello all, I'm building a small loopback test setup, where I output data coming from a data pattern generated to a pair of LVDS signals (data & clock) and receive those same signals in another ...
Altera_ForumHonored Contributor
Honored ContributorHi,
Just wonder if you are using separate TX only and RX only ALTLVDS? If yes, probably the issue is due to PLL sharing or limited PLL resource. You can try to use duplex mode ALTLVDS to see if can pass the compilation.
