PLL Issues

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Hi,

In my code, I need to do 10MHz to 50MHz PLL and transfer the output to about 10 internal modules. Is it customary and synthesizable? Is there any restriction for Altera PLL fun out

Can I use direct PLL conversion from 10MHz to 50MHz or should I use PLL to about 100MHz and then use Freq divider to 50MHz. What is your recommendation?

Thanks,

Idan

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Try 10 => 50MHz PLL then connect 50Mhz to all 10 modules and see if tool is happy. If you run into fanout problems then get several pll outputs at 50MHz.

avoid frequency division in logic.

Why for ALTPLL if clock multiplication factor =1 and clock division factor =1, then timings are met.

But if I change: multiplication factor =9 and clock division factor =10, then the timings ( of the schematic, that follows ALTPLL ) are not met although the resulting clock is even lower, then the original.

P.S. SDC file contains:

derive_pll_clocks

derive_clock_uncertainty

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Why for ALTPLL if clock multiplication factor =1 and clock division factor =1, then timings are met.

But if I change: multiplication factor =9 and clock division factor =10, then the timings ( of the schematic, that follows ALTPLL ) are not met although the resulting clock is even lower, then the original.

P.S. SDC file contains:

derive_pll_clocks

derive_clock_uncertainty

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just a guess. It could be that clock jitter gets more such that it becomes in effect higher than first case. Or it could be your design has multiple clock domains. or it is bad marginal design coincidence.

Clock jitter gets becomes higher just because of the fractional resulting multiplication factor 9/10 ?

Yes, my design has DCFIFO for clock domains crossing and the issue has a stable effect.

Are fractional multiplication factors ( 9/10 and alike ) no good to be used for clock domains crossing?

Or maybe some tuning in ALTPLL can fix it?

for jitter I assume the tool may report the achieved value. so I don't know for sure, just a guess.

With dc fifo you certainly got an issue to look at as possible reason especially if your timing slack at fifo was too small to begin with.

Transfers between clocks with non-integer factors are hard (or virtually impossible) to meet timing.

If you think about the possible clock edges of those two clocks, you'll see that some inevitably,< sometimes the edges will be damn close together.

For such cases, when the tools can't ensure the timing is met, the usual method is to handle them as asynchronous and live with the possible cases of metastability. (Use a DCFIFO with 2 or more stages).

That said, ou just wanted a 10 MHz and a 50 MHz clock. Hoyw come you ended up having a 9/10 factor?