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Altera_Forum
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13 years ago

PLL Issues

Hi, In my code, I need to do 10MHz to 50MHz PLL and transfer the output to about 10 internal modules. Is it customary and synthesizable? Is there any restriction for Altera PLL fun out Can...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

Clock jitter gets becomes higher just because of the fractional resulting multiplication factor 9/10 ?

Yes, my design has DCFIFO for clock domains crossing and the issue has a stable effect.

Are fractional multiplication factors ( 9/10 and alike ) no good to be used for clock domains crossing?

Or maybe some tuning in ALTPLL can fix it?