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Altera_Forum
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13 years ago

PLL Issues

Hi, In my code, I need to do 10MHz to 50MHz PLL and transfer the output to about 10 internal modules. Is it customary and synthesizable? Is there any restriction for Altera PLL fun out Can...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

You can check which paths fail timing and that should give you a clue.